1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor memory device, and more particularly, to a semiconductor memory device having a self-aligned contact capable of forming a storage node contact in a self-aligned manner, and a fabricating method thereof.
2. Description of the Related Art
In recent years, as semiconductor devices became highly integrated, the cell size occupied by a memory cell per unit area has been sharply reduced. Specifically, the cell size of a dynamic random access memory (DRAM) has been reduced to 1.5 xcexcm2 or less. Reduction in the cell size can be attained by reducing the gap between conductive layers constituting a cell. In particular, in DRAMs, due to their high integration, the gap between gate electrodes is continuously reduced to reach a minimum feature size based on a design rule. A contact hole for forming a contact between a bit line and a drain region (to be referred to as a xe2x80x9cbit line contactxe2x80x9d or xe2x80x9cdirect contact (DC)xe2x80x9d hereinafter), or a contact between a storage electrode and a source region (to be referred to as a xe2x80x9cstorage node contactxe2x80x9d or xe2x80x9cburied contact (BC) hereinafter) is continuously reduced to a minimum feature size.
As semiconductor devices become highly integrated, the distances between a contact hole for connecting a lower interconnection and an upper interconnection and adjacent interconnections decrease and the aspect ratio of the contact hole also increases. Therefore, when a contact hole is formed using a photolithography process in a highly integrated semiconductor device having a multi-layer interconnection structure, there is a limit in realizing a desired process in a reproducible manner. Accordingly, in order to overcome the limit of the photolithography process, a process of forming a contact hole in a self-aligned manner has been developed.
In a capacitor over bit line (COB) structure in which a capacitor is formed after forming a bit line, a storage node contact for connecting a storage electrode of a capacitor and an active region of a semiconductor substrate must be formed between bit lines. In the case where the storage node contact is formed in a contact type, shorts between the storage node contact and the bit lines cannot be avoided in a design rule of 0.2 xcexcm or less. In order to prevent shorts between a storage node contact and bit lines, a process of forming a self-aligned contact after capping the bit lines with nitride, which is disclosed in U.S. Pat. No. 5,879,986. According to this method, in a state where bit lines are formed and then a nitride layer is deposited over the entire surface of the resultant structure, the gap between the bit lines is filled with an oxide layer and then a contact hole is formed in a self-aligned manner.
However, according to this method, since a nitride layer for a spacer is further deposited in a state where the gap between bit lines is narrow, voids may occur during filling the gap between bit lines with an oxide layer, that is, a gap-filling capacity is degraded. Also, since the oxide layer between bit lines is formed over the nitride layer, the overall thickness of the nitride and oxide layers is greater than the narrow gap between bit lines, that is, the aspect ratio increases, thereby disabling formation of a self-aligned contact hole. Further, during an etching process for forming a self-aligned contact, after the oxide layer is etched and the nitride is then etched, an oxide layer under the bit lines should be additionally etched.
To solve the above problems, it is an object of the present invention to provide a highly integrated semiconductor memory device capable of easily filling the gap between bit lines and having a self-aligned contact between the bit lines. It is another object of the present invention to provide a method of fabricating a semiconductor memory device capable of easily filling the gap between bit lines and having a self-aligned contact between the bit lines.
Accordingly, to achieve the first object, there is provided a semiconductor memory device having a self aligned contact including a plurality of gate electrodes which are formed on a semiconductor substrate in a predetermined direction at constant intervals, a first insulating layer which is formed on the resultant structure having the gate electrodes and which has one or more of each of first and second openings which partially open an active region of the semiconductor substrate, first and second conductive pad layers which fill the first and second openings, a first interlayer dielectric film formed on the first insulating layer having the first and second pad layers, a plurality of bit lines which are orthogonal to the gate electrodes on the first interlayer dielectric film and are electrically connected to the first pad layer through the first interlayer dielectric film, insulating spacers formed at both side walls of the bit lines, a second interlayer dielectric film which is formed on the first interlayer dielectric film having the bit lines and the insulating spacers, and a storage electrode of a semiconductor capacitor, which is self-aligned to the insulating spacers between the bit lines and electrically connected to the second pad layer through the second interlayer dielectric film and the first interlayer dielectric film.
Preferably, a mask layer and insulating spacer are further formed on the gate electrode and at side walls thereof, respectively, and the first and second pad layers are self-aligned to the spacers. Also, the top surface levels of the first and second pad layers are as high as or lower than the top surface level of the mask layer on the gate electrode.
Also, the mask layer may be formed of a silicon nitride (SiN) layer based on plasma enhanced chemical vapor deposition (PECVD) or a thermal SiN layer and the insulating spacer formed at side walls of the bit line may be formed of a SiN layer based on low pressure chemical vapor deposition (LPCVD).
Preferably, the first and second interlayer dielectric films are formed of silicon oxide, and the insulating spacer formed at side walls of the bit line are formed of silicon nitride.
To achieve the second object, there is provided a method of fabricating a semiconductor memory device having a self-aligned contact, including the steps of forming a plurality of gate electrodes by interposing a gate insulating layer on an active region of a semiconductor substrate in a predetermined direction at constant intervals, forming a first insulating layer on the resultant structure having the gate electrodes and then forming one or more of each of first and second openings which partially open an active region of the semiconductor substrate, forming first and second pad layers by filling the first and second openings with a conductive material, forming a first interlayer dielectric film on the first insulating layer having the first and second pad layers and forming a third opening which opens the surface of the first pad layer, forming a plurality of bit lines in a direction orthogonal to the gate electrodes on the first interlayer dielectric film while filling the third opening, depositing an insulating layer on the resultant structure having the bit lines and removing the insulating layer on the bit lines and on the first interlayer dielectric film to form insulating spacers only at both side walls of the bit lines, forming a second interlayer dielectric film on the resultant structure having the insulating spacers and forming a fourth opening self-aligned to the insulating spacers to open the surface of the second pad layer, and filling the fourth opening with a conductive material.
The step of forming the bit lines preferably includes the sub-steps of forming a conductive layer on the first interlayer dielectric film while filling the third opening, forming a mask layer on the conductive layer and sequentially patterning the mask layer and the conductive layer.
The mask layer is preferably formed of a silicon nitride (SiN) layer based on plasma enhanced chemical vapor deposition (PECVD) or a thermal SiN layer. The first and second interlayer dielectric films are preferably formed of silicon oxide, and the insulating spacer formed at both side walls of the bit line are formed of silicon nitride.
Also, the fourth opening is preferably etched using a mixed gas of C4F8, O2 and Ar as an etching gas.
According to the present invention, when forming an opening for a storage node contact by anisotropically etching the second interlayer dielectric film and the first interlayer dielectric film, the opening can be formed to be self-aligned to the spacer formed at the side walls of the bit line. Also, since the gap between bit lines is wider than that in the conventional art, it is easy to fill the gap with the second interlayer dielectric film. Further, when forming an opening for a storage node contact, since the first interlayer dielectric film is continuously removed after etching the second interlayer dielectric film, the fabrication process can be simplified.